One of the most difficult and time-consuming steps in the design of any system on chip (SOC) verification is firmware code coverage. The more complex the chip, the more difficult and time consuming the code-coverage task. Further adding to this, if the firmware is “embedded” within the SOC, then code coverage becomes even more complex and complicated.
Code coverage analysis includes finding areas of a program not exercised by a set of test cases, creating additional test cases to increase coverage, and determining a quantitative measure of code coverage, which is an indirect measure of quality. An optional aspect of code coverage analysis is identifying redundant test cases that do not increase coverage. Coverage analysis is critical and important for complex system-on-chip verification and assures quality of set tests.
Embedded code-coverage has been done in simulations. As designs get bigger and users integrate more large blocks together to create huge SOCs, simulation time becomes unbearably long. Simulations can sometimes take in the order of several weeks. Some existing coverage analysis techniques access test program source code and often recompile it with a special command. This requires additional memory within the chip as the test cases are compiled along with “actual” firmware. This requires also more memory for this “virtual” code and drives up the cost of the SOC.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments presented in the remainder of the present application with references to the drawings.